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enpirion ? power datasheet en63a0q a 12a powersoc highly integrated synchronous buck with integrated inductor description the en63a 0qa is a 12a power system on a chip (powersoc) dc to dc converter with an integrated inductor, pwm controller, mosfets and compensation to provide the smallest solution size in a 10x11x3mm 76- pin qfn module. the EN63A0QA is aec - q100 qualified for automotive applications and is specifically designed to meet the precise voltage and fast transient requirements of high - performance, low - power processor, dsp, fpga, memory boards and system level applications in distributed power architecture. the en63a 0qa features switching freque ncy synchronization with an external clock or other en63a 0qa s for parallel operation . other features include precision enable threshold , pre - bias monotonic start - up, and programmable soft -start. the device?s advanced circuit techniques, ultra high switching frequency, and proprietary integrated inductor technology deliver high - quality, ultra compact, non - isolated dc - dc conversion. the altera enpirion integrated inductor solution significantly helps to reduce noise. the complete power converter solution enhances productivity by offering greatly simplified board design, layout and manufacturing requirements. all altera enpirion products are rohs compliant and lead - free manufacturing environment compatible. features ? high efficiency (up to 96% ) ? - 40 c to + 105c ambient temperature range ? ae c- q100 qualified for automotive applications ? cispr 25 6.6 / iso11452 -5 compliant ? excellent ripple and emi performance ? up to 12a continuous operating current ? input voltage range (2.5v to 6.6v) ? frequency synchronization (clock or primary) ? 2% v out accuracy (over line/load/temp erature ) ? optimized total solution size ( 2 80mm 2 ) ? precision e nable threshold for sequencing ? programmable soft - start ? master/slave configuration for parallel operation ? thermal shutdown, over -c urrent, short circuit, and under - voltage protection ? rohs compliant, msl l evel 3, 260 c r eflow applications ? automotive applications ? point of l oad r egulation for l ow -p ower , asics m ulti -c ore and c ommunication processors, dsps, fpgas and distributed power architectures ? high e fficiency 12v i ntermediate bus a rchitectures ? beat f requency/ noise sensitive applications v out v in 2x 47f 1210 vout enable agnd ss pvin avin pgnd pgnd EN63A0QA 15nf vfb r a r b r 1 c a fqadj 3x 47f 1210 r fqadj figure 1 . simplified applications circuit figure 2. highest efficiency in smallest solution size 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 9 10 11 12 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v vout = 1.2v conditions v in = 5.0v actual solution size 280mm 2 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA ordering information part number package markings temp rating (c) package description en63a 0qa en63a 0qa - 40 to + 105 76 - pin ( 10 mm x 11mm x 3mm) qfn t&r evb - en63a 0qa en63a 0qa qfn evaluation board packing and marking information : www.altera.com/support/reliability/packing/rel - packing - and- marking.html pin assignments (top view) nc 1 nc nc nc nc nc nc nc nc nc nc nc nc nc 2 3 4 5 6 7 8 9 vout vout nc vout vout vout vout vout vout vout nc nc(sw) nc(sw) pgnd pgnd pgnd pgnd pgnd pgnd pgnd pvin pvin pvin pvin pvin pvin pvin pvin pvin vddb nc bgnd nc s_in nc nc nc nc nc nc(sw) nc(sw) fqadj en_pb nc vsense ss eaout vfb m/s agnd avin enable pok s_out 10 11 12 13 14 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 56 55 54 53 52 51 50 49 48 47 46 45 44 43 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 77 pgnd keep out keep out keep out nc nc nc nc 15 16 17 18 pvin pvin pvin pvin 42 41 40 39 figure 3 : pin out diagram (top view) note a : nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. note b : shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the pcb. refer to figure 11 for details. note c : white ?dot? on top left is pin 1 indicator on top of the device package . pin description pin nam e function 1 - 1 9 , 2 9 , 52- 53, 67, 72 - 76 nc no connect: these pins must be soldered to pcb but not electrically connected to each other or to any external signal, voltage, or ground. these pins may be connected internally. failure to follow this guideline may result in device damage. 2 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA pin nam e function 20- 28 vout regulated converter output. connect to the load and place output filter capacitor(s) between these pins and pgnd pins 32 to 35. 30- 31, 70- 71 nc(sw) no connect: these pins are internally connected to the common switching node of the internal mosfets. they must be soldered to pcb but not be electrically connected to any external signal, ground, or voltage. failure to follow this guideline may result in device damage. 32- 38 pgnd input and o utput power ground. connect these pins to the ground electrode of the input and output filter capacitors. refer to vout , pvin descriptions and layout recommendation for more details. 39- 51 pvin input power supply. connect to input power supply and place input filter capacitor(s) between these pins and pgnd pins 3 6 to 3 8 . 54 vddb internal regulated voltage used for the internal control circuitry. decouple with a n optional 0.1 f capacitor to bgnd for improved efficiency. this pin may be left floating if board space is limited. 55 bgnd ground for vddb. refer to pin 46 description. 56 s_in digital i nput. a high level on the m/s pin will make this en63a 0qa a slave and the s_in will a ccept the s_out signal from another en63 a 0qa for parallel operation . a low level on the m/s pin will make this device a master and the switching frequency will be phase locked to an external clock. leave this pin floating if it is not used . 57 s_out digital o utput. a low level on the m/s pin will make this en63a 0qa a mast er and the internal switching pwm signal is output on this pin. this output signal is connected to the s_in pin of another en63a 0qa device for parallel operation. leave this pin floating if it is not used. 58 pok pok is a logic level high when vout is within - 10% to +20% of the programmed output voltage (0.9v out_nom v out 1.2v out_nom ). this pin has an internal pull - up resistor to avin with a nominal value of 94 k. 3 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA absolute maximum ratings caution : absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute maximum ratings may impair de vice life. exposure to absolute maximum rated conditions for extended periods may affect device reliability. param eter sym bol min m ax units voltages on : pvin, avin, vout - 0.3 7.0 v voltages on: en, pok, m/s - 0.3 v in +0.3 v voltages on: vfb , extref, eaout, ss, s_in, s_out, fqadj - 0.3 2.5 v storage temperature range t stg - 65 150 c maximum operating junction temperature t j- abs max 150 c reflow temp, 10 sec, msl3 jedec j - std - 020a 260 c esd rating (based on h uman b ody m odel ) 2000 v esd rating (based on cdm) 500 v recommended operating conditions param eter sym bol min m ax units input voltage range v in 2.5 6.6 v out put voltage range ( note 1 ) v out 0.60 v in ? v do v out put current i out 12 a operating ambient temperature t a - 40 + 105 c operating junction temperature t j - 40 +125 c thermal characteristics param eter sym bol typ units thermal resistance: junction to ambient (0 lfm) ( note 2 ) ja 1 4 c/w thermal resistance: junction to case (0 lfm) jc 1.0 c/w thermal shutdown t sd 150 c thermal shutdown hysteresis t sdh 20 c note 1 : v do (dropout voltage) is defined as (i load x dropout resistance). please refer to electrical charac t eristics table. note 2 : based on 2oz. external copper layers and proper thermal design in line with eij/jedec jesd51 -7 standard for h igh thermal conductivity boards. 4 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA electrical characteristics note: v in = 6.6 v , minimum and m aximum values are over operating ambient temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ m ax units operating input voltage v in 2. 5 6.6 v vfb pin voltage v vfb internal v oltage r eference at: v in = 5v, iload = 0 , t a = 25c 0.594 0.600 0.606 v vfb pin voltage (line, load and temperature) v vfb 2. 5 v v in 6.6v 0a i load 12a 0.588 0.600 0.612 v vfb pin input leakage current i vfb vfb p in i nput l eakage c urrent - 0.2 0.2 p a shut - down supply current i s power supply c urrent with e nable =0 1.5 ma under voltage lock - out ? v in rising v uvlor voltage a bove w hich uvlo is n ot a sserted 2.2 v under voltage lock - out ? v in falling v uvlof voltage b elow w hich uvlo is a sserted 2.1 v drop o ut voltage v do v inmin ? v out at full l oad 6 00 1200 mv drop o ut resistance (note 4) r do input to o utput r esistance 50 100 m c ontinuous output current i out_src refer to table 2 for conditions . subject to de - rating 0 12 a over current trip level i ocp sourcing c urrent 1 8.5 a switching frequency f sw r fadj = 4.42 k : v in = 5v 0.9 1.2 1.5 mhz external sync clock frequency lock range f pll_lock sync c lock i nput f requency r ange 0.9*f sw f sw 1.1*f sw mhz s_in clock amplitude ? low v s_in_lo sync clock l ogic low 0 0.8 v s_in clock amplitude ? high v s_in_hi sync clock l ogic high 1.8 2.5 v s_in clock duty cycle (pll) dc s_inpll m/s pin float or low 20 80 % s_in clock duty cycle (pwm) dc s_inpwm m/s pin high 10 90 % pre - bias level v pb allowable p re - bias as a f raction of p rogrammed o utput v oltage for m onotonic start up. minimum p re - bias v oltage = 300mv. 20 75 % non - monotonicity v pb_nm allowable n on - monotonicity u nder p re - bias s tartup 100 mv v out range for p ok = high range of o utput v oltage as a f raction of p rogrammed v alue w hen p ok is a sserted . ( note 3 ) 90 120 % 5 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA parameter symbol test conditions min typ m ax units p ok deglitch delay falling e dge d eglitch d elay a fter o utput c rossing 90% l evel . f sw =1. 2 mhz 213 s v pok logic low level with 4ma c urrent s ink into p ok p in 0.4 v v pok logic high level v in v pok internal pull - up resistor 94 k ? current balance ? i out with 2 to 4 c onverters in p arallel, the d ifference b etween n ominal and a ctual c urrent l evels. ? v in <50mv; r trace < 10 m ? , i load = # c onverter * i max +/ - 10 % v out rise time accuracy ? t rise (note 4) t rise [ms] = c ss [nf] x 0.065 ; q)?& ss ? 30nf; (note 5 and note 6) - 25 +25 % enable logic high v enable _high 9?9 in ? v ; 1. 2 v in v enable logic low v enable_low 0 0. 8 v e nable pin current i en v in = 6.6 v 50 4, 4v < v in ? 6.6v, r ext = 51k 117 88 a binary pin logic low threshold v b- low enable, s_in 0.8 v binary pin logic high threshold v b- high enable, s_in 1.8 v s_out low level v s_out_low 0.4 v s_out high level v s_out_high 2.0 v note 3 : pok threshold when vout is rising is nominally 92%. this threshold is 90% when vout is falling. after crossing the 90% level, there is a 256 clock cycle (~213s at 1 .2 mhz) delay before pok is de - asserted. the 90% and 92% levels are nominal values. expect these thresholds to vary by 3%. note 4 : parameter not production tested but is guaranteed by design. note 5 : rise time calculation begins when avin > v uvlo and e nable = high. note 6 : v out rise time accuracy does not include soft - start capacitor tolerance. . note 7 : m/s pin is ternary. ternary pins have three logic l evels: high, float, and low. th i s pin is meant to be strapped to vin through an external resistor, strapped to gnd, or left floating. the state cannot be changed while the device is on. 6 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA typical performance curves 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 9 10 11 12 efficiency (%) output current (a) efficiency vs. output current vout = 2.5v vout = 1.8v vout = 1.2v vout = 1.0v oitios v i = .v 0 10 20 0 0 50 0 0 80 0 100 0 1 2 5 8 10 11 12 ii (%) outut ut (a) efficiency vs. output current vout = 3.3v vout = 2.5v vout = 1.8v vout = 1.2v vout = 1.0v conditions v in = 5.0v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 1 2 3 4 5 6 7 8 9 10 11 12 output voltage (v) output current (a) output voltage vs. output current vout = 1.8v conditions v in = 3.3v 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 1 2 3 4 5 6 7 8 9 10 11 12 output voltage (v) output current (a) output voltage vs. output current vout = 1.0v conditions v in = 3.3v 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 0 1 2 3 4 5 6 7 8 9 10 11 12 output voltage (v) output current (a) output voltage vs. output current vout = 3.3v conditions v in = 5.0v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 1 2 3 4 5 6 7 8 9 10 11 12 output voltage (v) output current (a) output voltage vs. output current vout = 1.8v conditions v in = 5.0v 7 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA typical performance c urves (continued) 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 1 2 3 4 5 6 7 8 9 10 11 12 output voltage (v) output current (a) output voltage vs. output current vout = 1.0v conditions v in = 5.0v 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.4 3 3.6 4.2 4.8 5.4 6 6.6 output voltage (v) input voltage (v) output voltage vs. input voltage conditions load = 0a 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.4 3 3.6 4.2 4.8 5.4 6 6.6 output voltage (v) input voltage (v) output voltage vs. input voltage conditions load = 4a 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.4 3 3.6 4.2 4.8 5.4 6 6.6 output voltage (v) input voltage (v) output voltage vs. input voltage conditions load = 8a 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.4 3 3.6 4.2 4.8 5.4 6 6.6 output voltage (v) input voltage (v) output voltage vs. input voltage conditions load = 12a 1.188 1.190 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 -40 -15 10 35 60 85 110 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 2a load = 4a load = 6a load = 8a load = 10a load = 12a conditions v in = 3.6v v out_nom = 1.2v 8 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA typical performance curves (continued) 1.188 1.190 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 -40 -15 10 35 60 85 110 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 2a load = 4a load = 6a load = 8a load = 10a load = 12a conditions v in = 5v v out_nom = 1.2v 1.188 1.190 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 -40 -15 10 35 60 85 110 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 2a load = 4a load = 6a load = 8a load = 10a load = 12a conditions v in = 6.6v v out_nom = 1.2v 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 55 60 65 70 75 80 85 90 95 100 105 maximum output current (a) ambient temperature ( c) output current de - rating vout = 1.0v vout = 1.8v vout = 2.5v conditions v in = 3.3v t jmax = 125 c output current de - rating vout = 1.0v vout = 1.8v vout = 2.5v vout = 3.3v conditions v in = 5.0v t jmax = 125 c emi performance (horizontal scan) conditions v in = 5.0v v out_nom = 1.5v load = 0.14 emi performance (vertical scan) conditions v in = 5.0v v out_nom = 1.5v load = 0.14 10398 october 7, 2014 rev a
EN63A0QA typical parallel performance curves (continued) -5 -4 -3 -2 -1 0 1 2 3 4 5 2 4 6 8 10 12 14 16 18 20 22 24 current mis - match (%) output current (a) parallel current share mis - match mis-match (%) = (i_master - i_slave ) / i_average x 100 oitios a0a v i = 5v v out = .v 0 2 8 10 12 1 2 8 10 12 1 1 18 20 22 2 iiviua outut ut (a) tota outut ut (a) parallel current share breakdown master device slave device conditions EN63A0QA v in = 5v v out = 3.3v 10 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA typical performance characteristics vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 5v vout = 1v iout = 12a cin = 2 x 47f ( 1210) cout = 3 x 47 f ( 1210) vout (ac coupled) output ripple at 500mhz bandwidth conditions vin = 5v vout = 1v iout = 12a cin = 2 x 47f ( 1210) cout = 3 x 47 f ( 1210) vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 5v vout = 2.4v iout = 12a cin = 2 x 47f ( 1210) cout = 3 x 47 f ( 1210) vout (ac coupled) output ripple at 500mhz bandwidth conditions vin = 5v vout = 2.4v iout = 12a cin = 2 x 47f ( 1210) cout = 3 x 47 f ( 1210) enable enable power up/down conditions vin = 5v vout = 1.0v iout = 12a css = 15nf cin = 2 x 47f ( 1210) cout = 3 x 47 f ( 1210) vout enable enable power up/down conditions vin = 5v vout = 2.4v iout = 12a css = 15nf cin = 2 x 47f ( 1210) cout = 3 x 47 f ( 1210) vout 11 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA typical performance characteristics (continued) enable enable/disable with pok conditions vin = 5 v, v ou t = 1.0v load = 5 a, css = 15nf vout pok load vout (ac coupled) load transient from 0 to 12a conditions vin = 6.2v vout = 1.5v cin = 2 x 47f ( 1210) cout = 3 x 47f ( 1210 ) load parallel operation sw waveforms conditions vin = 5v vout = 1.8v load = 18a combined load(18a) master vsw slave 2 vsw slave 1 vsw parallel operation current sharing conditions vin = 5v vout = 1.8v load = 18a slave 1 load = 6a slave 2 load = 6a total load = 18a master load = 6a 12 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA functional block diagram soft start power good logic bandgap reference mux compensation network thermal limit uvlo current limit p-drive n-drive pll/sawtooth generator fqadj enable ss agnd pok vsense vfb pgnd s_out nc(sw) pvin to pll error amp pwm comp (+) (-) (-) (+) digital i/o s_in m/s vddb vout avin avin en_pb reference voltage selector eaout eaout mux avin avin bgnd eff 94k 24k 24k figure 4 : functional block diagram 13 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA functional description the en63a 0qa is a synchronous, programmable b uck power supply with integrated power mosfet switches and integrated inductor. the switching supply uses voltage mode control and a low noise pwm topology. t his provides superior impedance matching to ics processed in sub 90nm process technologies. the nominal input voltage range is 2.5 - 6.6 volts. the output voltage is programmed using an external resistor divider network. the feedback control loop incorpora tes a type iv voltage mode control design. type iv voltage mode control maximizes control loop bandwidth and maintains excellent phase margin to improve transient performance. the en63a 0qa is designed to support up to 12a continuous output current operation. the operating switching frequency is between 0.9mhz and 1.5mhz and enables the use of small - size input and output capacitors. the power supply has the following features: ? precision e nable t hreshold ? soft -s tart ? pre -b ias s tart -up ? resistor p rogrammable s witching f requency ? phase -lock f requency synchronization ? parallel op eration ? power ok ? over-c urrent /short circuit p rotection ? thermal s hutdown with hysteresis ? under -v oltage l ockout precision enable the enable threshold is a precision a nalog voltage rather than a digital logic threshold. a precision voltage reference and a comparator circuit are kept powered up even when enable is de- asserted. the narrow voltage gap between enable logic low and enable logic high allows the device to turn on at a precise enable voltage level. with the enable threshold pinpointed, a proper choice of soft - start capacitor helps to accurately sequence multiple power supplies in a system as desired. there is an enable lockout time of 2ms that prevents the device from re - enabling immediately after it is disabled. soft-start the ss pin in conjunction with a small external capacitor between this pin and agnd provides a soft- start function to limit in - rush current during device power - up. when the part is initially powered up, the output voltage is gradually ramped to its final value. the gradual output ramp is achieved by increasing the reference voltage to the error ampl ifier. a constant current flowing into the soft - start capacitor provides the reference voltage ramp. when the voltage on the soft - start capacitor reaches 0.60v, the output has reached its programmed voltage. once the output voltage has reache d nominal voltage the soft - start capacitor will continue to charge to 1.5v (typical) . the output rise time can be controlled by the choice of soft - start capacitor value. the rise time is defined as the time from when the e nable signal crosses the threshold and the inpu t voltage crosses the upper uvlo threshold to the time when the output voltage reaches 95% of the programmed value. th e rise time (t rise ) is given by the following equation: t rise [ms] = c ss [nf] x 0.065 the rise time (t rise ) is in milliseconds and the soft- start capacitor (c ss ) is in nano -f arads. the soft - start capacitor should be between 10 nf and 100nf. pre- bias start -up the en63a 0qa supports startup into a pre - biased load. a proprietary circuit ensures the output voltage rise s up from the pre - bias value to the programmed output voltage. start - up is guaranteed to be monotonic for pre - bias voltages in the range of 20% to 75% of the programmed output voltage with a minimum pre - bias voltage of 300mv. outside of the 20% to 75% range, the output voltage rise will not be monotonic. the pre - bias feature is automatically engaged with an internal pull - up resistor. for this feature to work properly, v in must be ramped up prior to enable turning on the device. tie vsense to vout if pre - bias is used. tie en_pb to ground and leave vsense floating to disable the pre - bias feature. pre - bias is supported for external clock synchronization, but not supported for parallel operations. resistor programmable frequency the operation of the en63a 0qa can be optimized by a proper choice of the r fqadj resistor. the f requency can be tuned to optimize dynamic performance and efficiency. refer to table 1 and table 2 for recommended r fqadj values based on maximum output current operations . 14 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA table 1: recomme nded r fqadj (k ? ) at 10a v out v in 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v 3.3v table 2 : recommended r fqadj (k ? ) at 1 2a v out v in 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v 3.3v phase - lock operation: the en63a 0qa can be phase - locked to an external clock signal to synchronize its switching frequency. t he m/s pin can be left floating or pulled to ground to allow the device to synchronize with an external clock signal using the s_in pin. when a clock signal is present at s_in, an activity detector recognizes the presence of the clock signal and the internal oscillator phase locks to the external clock. the external clock could be the system clock or the output of another en63a 0qa. t he phase lo cked clock is then output at s_out . refer to table 2 for recommended clock frequencies. mast er / slave (parallel) operation and frequency synchronization multiple en63a 0qa devices may be connected in a master/slave configuration to handle larger load currents. the device is place d in master mode by pulling the m/s pin low or in slave mode by pulling m/s pin high. when t he m/s pin is in f loat state, parallel operation is not possible. in m aster mode, a version of the internal switching pwm signal is output on the s_out pin. this pw m signal from the master is fed to the s lave device at its s_in pin . the slave device acts like an extension of the power fets in the master and inherit s the pwm frequency and duty cycle . the inductor in the s lave prevents crow - bar currents from master to s lave due to timing delays . the master device?s switching clock may be phase - locked to an external clock source or another en63a 0qa to move the entire parallel operation frequency away from sensitive frequencies . the feedback network for the slave device may be left open . additional slave devices may be paralleled together with the master by connecting the s_out of the master to the s_in of all other slave devices. refer to figure 5 for details. note that when combining multiple regulators together, the ma ximum current for each device should be kept under 80% of the maximum output current in order to margin for the current mis - match between each regulator. careful attention is needed in the layout for parallel operation. the vin, vout and gnd of the paralle led devices should have low impedance connections between each other. maximize the amount of copper used to connect these pins and use as many vias as possible when using multiple layers. place the master device between all other slaves and closest to the point of load. EN63A0QA master EN63A0QA slave1 s_out s_in s_in vout vout vout vin vin vin gnd gnd gnd vfb vfb vfb feedback & compensation open open open vin vout m/s m/s m/s EN63A0QA slave2 EN63A0QA slave3 s_in vout vin gnd vfb m/s r ext r ext r ext figure 5: master/slave parallel operation diagram pok operation the pok signals that the output voltage is within the specified range. the pok signal is asserted high when the rising output voltage crosses 92% (nominal) of the programmed output voltage. i f the output voltage falls outside the range of 90% to 120% , pok remains asserted for the de - glitch time (213s at 1.2mhz) . after the de - glitch time, pok is de- asserted. pok is also de- asserted if the output vol tage exceeds 120% of the programmed output 15 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA voltage. over current protection the current limit function is achieved by sensing the current flowing through a sense p - fet. when the sensed current exceeds the current limit, both power fets are turned off for the rest of the switching cycle. if the over - current condition is removed, the over - current protection circuit will re - enable pwm operation. if the over - current condition persists, the circuit will continue to protect the load. the ocp trip point is nomina lly set as specified in the electrical characteristics table. in the event the ocp circuit trips consistently in normal operation, the device enters a hiccup mode. the device is disabled for 27 ms and restarted with a normal soft - start. this cycle can conti nue indefinitely as long as the over current condition persists. thermal overload protection temperature sensing circuits in the controller will disable operation when the j unction temperature exceeds approximately 150oc. once the junction temperature drops by approx 20oc, the converter will re - start with a normal soft - start. input under - voltage lock - out when the input voltage is below a required voltage level (v uvhi ) for normal operation, the converter switching is inhibited. the lock - out threshold has hy steresis to prevent chatter. thus when the device is operating normally, the input voltage has to fall below the lower threshold (v uvlo ) for the device to stop switching. 16 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA application information output voltage programming and loop compensation the en63a 0qa output voltage is programmed using a simple resistor divider network. a phase lead capacitor plus a resistor are required for stabilizing the loop. figure 6 shows the required components and the equations to calculate their values. the en63a 0qa output voltage is determined by the voltage presented at the vfb pin. this voltage is set by way of a resistor divider between vout and agnd with the midpoint going t o vfb. the en63a 0qa uses a type iv compensation network. most of this network is integrated. however , a phase lead capacitor and a resistor are required in parallel with upper resistor of the external feedback network ( refer to figure 6 ). total compensati on is optimized for use with three 47f output capacitance and will result in a wide loop bandwidth and excellent load transient performance for most applications. additional capacitance may be placed beyond the voltage sensing point outside the control loop. voltage mode operation provides high noise immunity at light load. further more , v oltage mode control provides superior impedance matching to ics processed in sub 90nm technologies. in some cases modifications to the compensation or output capacitance may be required to optimize device performance such as transient response, ripple, or hold - up time. the en63a 0qa provides the capability to modify the control loop response to allow for customization for such applications. for more information, contact alte ra power applications support. vout vfb r a c a r1 r b figure 6 : external f eedback/ c ompensation n etwork the feedback and compensation network values depend on the input voltage and output voltage . calculate the external feedback and compensation network values with the equations below. r a [] = 48,400 x v in [v] *round r a up to closest standard value r b [] = (v fb x r a ) / (v out ? v fb ) [v] v fb = 0.6v nominal *round r b up to closest standard value c a [f] = 4.6 x 10 -6 / r a [] *round c a down to closest standard value r1 = 1 2 k the feedback resistor network should be sensed at the last output capacitor close to the device. keep the trace to vfb pin as short as possible. whenever possible, connect r b directly to the agnd pin instead of going through the gnd plane. input capacitor selection the en63a 0qa has been optimized for use with two 1210 47f or four 1206 22f input capacit ors . low esr ceramic capacitors are required with x7r dielectric formulation. y5v or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. in some applications, lower value ceramic capacitors may be needed in parallel with the larger capacitors in order to provide high frequency decoupling. t he capacitors shown in the table below are t ypical input capacitors. other capacitors with similar characteristics may also be used. table 3 : recommended input capacitors description mfg p/n 47f, 6.3v, x7r, 1210 murata grm32er70j476me20 taiyo yuden lmk325b7476km - tr 22f, 10v, x7r, 1206 murata grm31cr71a226me15 taiyo yuden lmk316ab7226kl - tr avx 1206zc226kat2a output capacitor selection the en63a 0qa has been optimized for use with three 1210 47 f or six 1206 22f output capaci tor s. low esr x7r ceramic capacitors are re commended as the primary choice . y5v or 17 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. the capacitors shown in the recommended output capacitors table a re t ypical output capacitors. other capacitors with similar characteristics may also be used. additional bulk capacitance from 100f to 1000f may be placed beyond the voltage sensing point outside the control loop. this additional capacitance should have a minimum esr of 6m to ensure stable operation. most tantalum capacitors will have more than 6m of esr and may be used without special care. adding distance in layout may help increase the esr be tween the feedback sense point and the bulk capacitors. tab le 4 : recommended output capacitors description mfg p/n 47f, 6.3v, x7r, 1210 murata grm32er70j476me20 taiyo yuden lmk325b7476km - tr 22f, 10v, x7r, 1206 murata grm31cr71a226me15 taiyo yuden lmk316ab7226kl - tr avx 1206zc226kat2a output ripple voltage is primarily determined by the aggregate output capacitor impedance. placing multiple capacitors in parallel reduces the impedance and hence will result in lower ripple voltage. n total zzzz 1 ... 111 21 table 5 : typical ripple voltages output capacitor configuration typical output ripple (mvp - p) 3 x 47 f < 5 mv ? 20 mhz bandwidth limit measured on evaluation board m/s - ternary pin m/s is a t ernary pin. this pin can assume 3 states ? a low state (0v to 0.7v), a high state (1.8v to vin) and a float state (1.1v to 1.4v) . device operation is controlled by the state of the pin. the pins may be pulled to ground or left floating without any special care . w hen pulling high to vin, a series resistor is recommended . the resistor value may be optimized to reduce the current drawn by the pin. the resistance should not be too high as in that case the pin may not recognize the high state. the recommend resistance (r e xt ) value is given in the following table . table 6 : recommended r ext resistor v in (v) i m ax (a) r ext (k) 2.5 ? 4 .0 117 15 4 .0 ? 6.6 88 51 2.5v to gates r ext r1 134k r2 134k to v in r3 319 d1 vf 2v inside EN63A0QA agnd m/s figure 7 : selection of r ext to connect m/s pin to v in table 7 : m/s (master/slave) pin states m/s pin function low (0v to 0.7v) m/s pin is pulled to ground directly. this is the master mode. switching pwm phase will lock onto s_in external clock if a signal is available. s_out outputs a version of the internal switching pwm signal . float (1.1v to 1.4v) m/s pin is left floating. parallel operation is not feasible. switching pwm phase will lock onto s_in external clock if a signal is available . s_out outputs a version of the internal switching pwm signal . high (> 1.8v ) m/s pin is pulled to vin with r ext . this is the slave mode. the s_in signal of the s l ave should connect to the s_out of the master device. this signal synchronize s the switching frequency and duty cycle of the master to the slave device. power - up sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. tying all three pins together meets these requirements. 18 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA thermal considerations thermal considerations are important power supply design facts that cannot be avoided in the real world. whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. the altera enpirion powersoc helps alleviate some of those concerns . the altera enpirion en63a 0qa dc -d c converter is packaged in a 10 x11 x3mm 76- pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (pcb) to act as a heat sink. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c may reduce long - term reliability. the device has a thermal overload protec tion c ircuit designed to turn off the device at an approximate junction temperature value of 150c. the following example and ca lculations illustrate the thermal performance of the en63a 0qa . example: v in = 5v v out = 1.8 v i out = 12a first calculate the output power. p ou t = 1.8 v x 12a = 21.6 w next, determine the input power based on the efficiency () shown in figure 8 . figure 8 : effi ciency vs. output current for v in = 5v, v out = 1.8 v at 12a , 85% = p out / p in = 87 % = 0. 85 p in = p out / p in 21.6 w / 0. 85 25. 41 w the power dissipation (p d ) is the power loss in the system and can be calculated by subtracting the output power from the input power. p d = p in ? p out 2 5.41 w ? 21.6 3.81 w with the power dissipation known , the temperature rise in the device may be estimated based on the t heta ja value ( ja ). the ja parameter estimates how much the temperature will rise in the device for every watt of power dissipation. the en63a 0qa has a ja value of 1 4 oc/w without airflow. determine the change in temperature (t) based on p d and ja . t = p d x ja t 3.81 w x 1 4 c/w = 53.36 c 53 c the junction temperature (t j ) of the device is approximately the ambient temperature (t a ) plus the change in temperature. we assume the initial ambient temperature to be 25c. t j = t a + t t j 25c + 53 c 78 c the maximum operating junction temperature (t j max ) of the device is 125c, so the device can operate at a higher ambient temperature. the maximum ambient temperature (t amax ) allowed can be calculated. t amax = t j max ? p d x ja 125 c ? 53 c 72c the maximum ambient temperature the device can reach is 72 c given the input and output conditions. note that the efficiency used in this example is at 85c ambient temperature and is a worst case condition. refer to the de - rating curves in the typical performance curves section. 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 9 10 11 12 efficiency (%) output current (a) efficiency vs. output current vout = 1.8v conditions v in = 5.0v t a = 85 c ~85% 19 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA engineering schematic figure 9: engineering schematic with engineering notes 20 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA layout recommendations figure 10: top layout with critical components only (top view) . see figure 9 for corresponding schematic this layout only shows the critical components and top layer traces for minimum footprint in single - supply mode with enable tied to avin. alternate circuit configurations & othe r low - power pins need to be connected and routed according to customer application. please see the gerber files at www.altera.com/enpirion for details on all layers. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en 63a 0qa package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the en 63a 0qa should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: the pgn d connections for the input and output capacitors on layer 1 need to have a slit between them in order to provide some separation between input and output current loops. recommendation 3 : the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and the input/output capacitors. re comme ndation 4 : the thermal pad underneath the component must be connected to the system ground plane through as many vias a s possible. the drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20 - 0.26mm. do not use thermal reliefs or spokes to connect the vias to the ground p lane. this connection provides the path for heat dissipation from the converter. re comme ndation 5 : multiple small vias (the same size as the thermal vias discussed in recommendation 4 ) should be used to connect ground terminal of the input capacitor and o utput capacitors to the system ground plane. it is preferred to put these vias along the edge of the gnd copper closest to the +v copper. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. recommendation 6 : avin is the power supply for the small - signal control circuits. it should be connected to the input voltage at a quiet point. in figure 10 this connection is made at the input capacitor. recommendation 7 : th e layer 1 metal under the device must not be more than shown in figure 10 . refer to the section regarding exposed metal on bottom of p ackage. as with any switch - mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. re comme ndation 8: the v out sense point should be just after the last output filter capacitor. keep the sense trace short in order to avoid noise coupling into the node. recommendation 9 : keep r a , c a , r b , and r 1 close to the vfb pin ( refer to figure 10 ). the vfb pin is a high - impedance, sensitive node. keep the trace to this pin as short as possible. whenever possible, connect r b directly to the agnd pin instead of going through the gnd plane. recommendation 10: follow all the layout recommendations as close as possible to optimize performance. altera provides schematic and layout reviews for all customer designs. design considerations for lead -frame based modules 21 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA expose d metal on bottom of package lead- frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead - frame cantilevers be exposed at the point where wire - bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package, as shown in figure 11 . only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the pc board. the pcb top layer under the en63a 0qa should be clear of any metal (copper pours, traces, or vias) excep t for the thermal pad. the ? shaded - out? area in figure 11 represents the area that should be clear of any metal on the top layer of the pcb. any layer 1 metal under the shade d- out area runs the risk of undesirable shorted connections even if it is covered by soldermask. the s older s tencil a perture should be smaller than the pcb ground pad. this will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package . please consult en63a 0qa qfn package soldering guidelines for more details and recommendations. figure 11 : lead- frame exposed metal (bottom view) shaded area highlights exposed metal that is not to be mechanically or electrically connected to the pcb. 22 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA recommended pcb footprint figure 12: EN63A0QA pcb footprin t ( top view) the solder stencil aperture for the thermal pad is shown in blue and is based on enpirion power product manufacturing specifications. 23 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA package and mechanical figure 1 3 : EN63A0QA package dimensions (bottom view ) packing and marking information : www.altera.com/support/reliability/packing/rel - packing - and- marking.html 24 www.altera.com/enpirion 10398 october 7, 2014 rev a
EN63A0QA contact information altera corporation 1 01 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 25 www.altera.com/enpirion 10398 october 7, 2014 rev a

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